1. Field of the Invention
This invention relates generally to serial-parallel-serial charge-coupled devices, and more particularly to a bidirectional device wherein serial streams of charge packets flow simultaneously in opposite directions through the parallel section.
2. Description of the Prior Art
Charge-coupled device (CCD) structures for use in data processing system storage and communication signal processing are well-known in the art. Referring to the patents and publications listed below under the heading "References Cited By Applicant", Boyle and Smith [Refs. 1, 2, 3] originally disclosed the basic charge-coupled concept. Weimer [Ref. 4] disclosed the serial-parallel-serial arrangement. Tompsett [Ref. 5] reviewed further early work, including the serial-parallel-serial configuration. Collins et al. [Ref. 6] disclosed a serial-parallel-serial structure with doublelevel metallization. Carnes, Kosonocky and Sauer [Refs. 7, 8] disclosed further advances including two-phase operation, buried channel structures, and applications to analog signal processing and image sensors.
In a serial-parallel-serial configuration, a data bit stream is injected into a serial CCD shift register from where it is transferred in parallel to a parallel storage section. The data can then be shifted in parallel through the parallel section, and then transferred in parallel to an output serial register, from where it is shifted out as a serial bit stream.
This serial-parallel-serial configuration had bit density limitations because charge-coupled devices require both transfer and storage sites. That is, in a two-phase serial shift register, the storage of one bit of information requires not only a storage site but also a transfer site so that bits are actually stored at one instant of time in only one-half of the available sites. For example, in a two-phase serial CCD with eight sites, only four bits can be stored. The parallel section was similarly limited in that the channel width was necessarily twice the width of a single site in the serial sections so that only one-half of the potentially available storage sites in the parallel section could be utilized.
Bit storage density was then significantly improved by the interlaced modification of the serial-parallel-serial configuration. In an interlaced version of the above example having eight sites and two-phase operation, all eight serial bits can be transferred in parallel through the parallel section, at least theoretically doubling the number of bits that can be stored in the parallel section. Embodiments of interlaced configuations are disclosed by Elmer et al. [Ref. 9, 10, 11], Kosonocky [Ref. 8], and Erb [Ref. 12].
Although the charge-coupled device structure is substantially simpler and therefore less expensive to manufacture than random access memory structures, the charge-coupled device operates in a serial access mode and is therefore substantially slower in operation. This is the major disadvantage of charge-coupled devices as compared with random access memory circuits.
The serial access aspect of charge-coupled devices is further aggravated by the alternate-cycle mode of operation of prior charge-coupled devices. That is, the requirement for alternating transfer and storage sites heretofore made it necessary to input and output the successive data bits at alternate clock cycles. For example, if the clock frequency were two megahertz then the data transfer rate would be only one megahertz.
This performance limitation of the prior art could not be obviated by simply increasing the clock frequency. The power dissipation of the device is approximately proportional to the clock frequency, in accordance with the formula: EQU Power=K.times.Capacitance.times.Voltage.sup.2 .times.Frequency
Therefore, for a given power dissipation the clock frequency is substantially predetermined, and any attempt to substantially increase the data transfer rate by increasing the clock frequency results in a proportionate increase in the power dissipation.